Level Shifts on the DieĪs an example, a microcontroller experiencing ground bounce may have its ground potential shifted such that the voltage measured between the power rail and ground is 1.5 V higher than the case without ground bounce. Because a real trace has these parasitics, they need to be included in the lumped RLC network formed by the trace, inductances at the driver's ground pin, and the load capacitance. Remember that all traces have some impedance due to their parasitic capacitance and inductance. When you look at the trace connecting the driving component to the capacitive load, the trace inductance and capacitance also influence how ground bounce affects your signals. However, when back EMF produced by ground bounce is large, especially when multiple outputs are switched simultaneously, the ground level of the device rises to a level that may affect other groups of pins on the IC. It will still occur, but it might be small enough as to go un-noticed. When ground bounce in a PCB is minimal, it may not cause any disruption to the die ground or signal behavior. How Ground Bounce in a PCB Affects Circuits and Signals This buildup is then damped due to the DC resistance of these elements and parasitics in the IC package/die. To better understand exactly how this affects signal behavior, it helps to understand that this arrangement of parasitics and the trace form an equivalent RLC circuit with some defined impedance and resonance frequency. This causes a phenomenon where the die-ground and the board ground are at different voltage levels for a momentary period, which results in ground bouncing noise. The total package inductance from these elements can be modeled as a set of inductors in series, as shown in the above schematic.Īs the current rushes through the inductance on the bond wire/lead frame/PDN, a back EMF builds up between the die-ground and the board ground. In a realistic design, however, some parasitic inductance is present between the die-ground and the board ground due to the bond wire, lead frame, and parasitic inductance in the PDN. In an ideal situation, the ground of the IC package and the board will remain at the same voltage. As the output buffer circuit is turned off to logic ‘0’, the capacitive load discharges to provide the inrush of current back to the driver this quick rush of current flows through the driver's ground pin. When the output pin is asserted to logic circuit ‘1’, the parasitic capacitance at the load is fully charged to VCC. In most high speed designs, the output pin of a driver circuit is usually connected to a load with some input capacitance. Ground bounce noise in a PCB is a difficult problem to measure, and the effects it has on power gating and signal integrity are related to the trace impedance and PDN impedance in a PCB. The image below shows a CMOS buffer circuit that forms the typical I/O in ICs like microcontrollers and random access memory (RAM). To understand ground bounce, you need to dive into the basics of a sleep transistor and ground pins that form the core of integrated circuits (IC). By taking ground bounce reduction techniques into consideration, you can minimize ground bounce in PCB signal integrity across your designs. To excel as a solid PCB layout engineer, being knowledgeable about the effects of ground bounce on circuits and signal integrity is necessary. Not understanding ground bounce in electronics, however, can be very problematic for your circuits. Not being able to bounce the basketball is one thing. I never really got into handling a basketball well, but in martial arts at least I could bounce off the balls of my feet to meet my opponent. While my dreams of becoming an NBA pro were dashed, I later discovered my passion for martial arts. Needless to say, I quit sports before I even started. Unlike my dad who thrived on the basketball team during his school days, I could barely bounce the ball during tryouts.
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